Complementary metal-oxide-semiconductor (CMOS) is a technology for constructing digital integrated circuits (IC) such as microprocessors, microcontrollers, and others, or analog circuits such as image sensors, data converters, and transceivers for many types of communication. An IC may comprise digital logic parts such as transistors, plus other components such as resistors and capacitors, connected together by metal layers.
Many kinds of capacitors such as metal-oxide-semiconductor (MOS) capacitors, PN junction capacitors, polysilicon-insulator-polysilicon (PIP) capacitors, and metal-insulator-metal (MIM) capacitors are used in semiconductor devices. In particular, the MIM capacitor offers reduced electrode resistance with wide ranges of applications.
A semiconductor chip may comprise of a plurality of contacts interconnected by multiple metal layers, which are separated by layers of insulating materials forming inter-metal dielectric (IMD) layers. Interconnections between different metal layers are made by vias, which go through insulating layers. Vias allow for communication between interconnects of other metal layers or directly with the semiconductor devices in the substrate. Typical chips may comprise of three or more metal layers, followed by a final passivation layer. The final passivation layer may be used for protecting the CMOS from mechanical abrasion during probe and packaging and to provide a barrier to contaminants. After the final passivation layer, the bond pads for input/output will be opened, followed by the normal post-fabrication process such as wafer probe, die separation, and packaging.
One way to fabricate layers of metal for a chip involves a damascene process. Damascene means formation of a patterned layer imbedded on and in another layer such that the top surfaces of the two layers are coplanar. An IMD is deposited either directly on a substrate, or on top of another existing layer of metal. Once the IMD is deposited, portions of the IMD may be etched away to form recessed features, such as trenches and vias, which can connect different regions of the chip and accommodate the conductive lines. A damascene process which creates either only trenches or vias is known as a single damascene process. A damascene process which creates both trenches and vias at once is known as a dual damascene process.
Damascene and dual-damascene processes use lower resistance metals (e.g. copper) to form many metal elements (e.g. lines, interconnects, and the like) instead of the conventionally used aluminum. A thin barrier film is used to prevent copper diffusion into the dielectric. As the number of interconnect levels increases, planarization of the previous layers is required to ensure a flat surface prior to subsequent lithography. Chemical mechanical planarization (CMP) is the primary processing method to achieve such planarization although dry etch back is still used sometimes.
MIM capacitors may be formed in different shapes such as cylindrical shape, a concave shape, a stacked shape, and so forth. Some current MIM capacitor fabrication method may have undesired impact on logic process like backend RC model change, IR drop along tall via and process reliability concern. There is a continuing need in the semiconductor device processing art for improved MIM capacitor structures and manufacturing processes.